Intel and ASML pass a million-wafer High-NA EUV mark
Intel and ASML report more than one million High-NA EUV wafers processed, but the total mixes testing, R&D and selected production layers.
Intel Foundry and ASML say they have processed more than one million wafers with High-NA EUV lithography, giving the chip industry a new, if incomplete, measure of how far the equipment has moved beyond lab work.
The companies disclosed the total on September 7 at the SPIE Photomask Technology + Extreme Ultraviolet Lithography conference. It combines tool certification, testing, research and development, plus production on selected layers of some Intel Core Ultra Series 3 processors, known as Panther Lake. The count does not mean one million commercial Panther Lake wafers were made with the technology.
High-NA EUV is a newer form of extreme-ultraviolet lithography. Its optics have a numerical aperture of 0.55, compared with 0.33 for ASML's established NXE machines. In practical terms, that can let a foundry pattern smaller features with fewer process steps, but only if masks, materials, inspection and yield control hold up in a production line.
A count with important limits
Intel and ASML say overlay, throughput and availability meet Intel Foundry's expectations. They did not publish yield, defect-density, uptime or throughput figures, nor did they split the million-wafer total between qualification work, research and commercial production. Those gaps make the figure a sign of operating experience rather than a direct measure of manufacturing economics.
Independent reporting by New-Tech Europe reached the same distinction: the total spans several kinds of wafer work and cannot establish how much was commercial production. That matters because a new lithography platform becomes useful to chip customers only when it can run repeatably at an acceptable cost.
Why the masks matter
The companies also described a near-term way to use High-NA tools with the current 6-inch photomask format. Designers can keep a layout inside the smaller exposure field or use reticle stitching, which joins exposures on a wafer. Intel says it is providing process-design-kit support for that route.
That workaround does not settle the industry's longer-term mask problem. On September 8, ASML and TSMC announced a separate initiative aimed at a 12-inch-mask pilot line by 2031 and advanced-node production by 2033. The companies describe those dates as targets, not completed infrastructure.
The million-wafer figure therefore says more about readiness than scale. Intel and ASML have shown that High-NA EUV can stay in an advanced manufacturing flow while using today's masks. The unanswered commercial questions are how many layers use it, what fraction of the count came from production, and whether the economics improve as more foundries adopt the platform.
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